Short Bio

Peilin (Leo) Chen is a Ph.D. candidate in the Electrical and Computer Engineering Department at the University of Virginia (UVA) under the supervision of Prof. Xiaoxuan Yang. His research focuses on designing energy-efficient algorithms, architectures, and systems for AI workloads, including CNNs, LLMs, and neuromorphic deep learning models.

Prior to UVA, he earned the B.E. degree from Xidian University (XDU) in 2024, majored in Integrated Circuit Design and Integration System. During his undergraduate, he worked with Prof. Kang Li on designing the 64-bit pipeline RISC-V processor.

Research Interests

AI Chip, Algorithm–Hardware Co-Design, Neuromorphic Computing, Computer Architecture

News

Selected Publications

Lonic: Algorithm-Hardware Co-Design for Energy-Efficient Fully Local Online SNN Training with INT4 Precision

Peilin Chen and Xiaoxuan Yang

ACM/IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, 2026.

Rank First in the Track

[paper]   [code]

SpikON: A Dual-Parallel and Efficient Accelerator for Online Spiking Neural Networks Learning

Peilin Chen and Xiaoxuan Yang

ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Evanston, Illinois, USA, 2026.

Invited for IEEE TVLSI Extension

[paper]   [code]

SpiKint: Native Full-Integer Spiking Neural Networks Training with an Efficient CIM-based Accelerator

Peilin Chen and Xiaoxuan Yang

ACM Great Lakes Symposium on VLSI (GLSVLSI), Finger Lakes, NY, USA, 2026.

[paper]   [code]

Titanus: Enabling KV Cache Pruning and Quantization On-the-Fly for LLM Acceleration

Peilin Chen and Xiaoxuan Yang

ACM Great Lakes Symposium on VLSI (GLSVLSI), New Orleans, USA, 2025.

Rank First in the Track · Best Paper Award

[paper]   [code]

Optimizing and Exploring System Performance in Compact Processing-in-Memory-Based Chips

Peilin Chen and Xiaoxuan Yang

IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Bordeaux, France, 2025.

[paper]   [code]