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Short Bio
Peilin (Leo) Chen is a second-year Ph.D. student in the ECE Department of the University of Virginia (UVA) under the supervision of Prof. Xiaoxuan Yang. He received the B.E. degree in Integrated Circuit Design and Integration System from Xidian University (XDU). His research focuses on algorithm-hardware co-design for efficient neural network inference and training.
News
May 2026
One first-authored paper has been accepted to IEEE/ACM ISLPED 2026 (Oral presentation)! See you in Evanston, Illinois, USA 🎉!
Apr 2026
One first-authored paper has been accepted to ACM GLSVLSI 2026! See you in Finger Lakes, NY, USA 🎉!
Jul 2025
Paper “Titanus: Enabling KV Cache Pruning and Quantization On-the-Fly for LLM Acceleration” wins Best Paper Award of GLSVLSI 2025 🎉!
Apr 2025
One first-authored paper has been accepted to ACM GLSVLSI 2025! See you in New Orleans, USA 🎉!
Apr 2025
Accepted as a DAC Young Fellow at the 62nd Design Automation Conference! See you in San Francisco, USA 🎉!
Dec 2024
One first-authored paper has been accepted to IEEE AICAS 2025! See you in Bordeaux, France 🎉!
Jun 2024
My dissertation, Design, logic synthesis and physical implementation of pipeline processor based on RISC-V architecture, has been selected as the excellent graduation project 🎉!
Feb 2024
I will be a Ph.D. student at the University of Virginia in Fall 2024 and have been awarded the UVA Provost's Fellowship 🎉!