Welcome to Peilin’s homepage!

 

Short Bio

Peilin (Leo) Chen is a second-year Ph.D. student in the ECE Department of the University of Virginia (UVA) under the supervision of Prof. Xiaoxuan Yang. He received the B.E. degree in Integrated Circuit Design and Integration System from Xidian University (XDU). His research interests are Digital/Mixed-signal IC Design, AI Chips Based on Computing-in-Memory, Software-Hardware Co-Design, Neuromorphic Computing, and Computer Architecture.

 

News

[2025.07] Paper "Titanus: Enabling KV Cache Pruning and Quantization On-the-Fly for LLM Acceleration" wins Best Paper Award of GLSVLSI 2025 πŸŽ‰!

[2025.04] One first-authored paper has been accepted to ACM GLSVLSI 2025! See you in New Orleans, USA πŸŽ‰!

[2025.04] Accepted as a DAC Young Fellow at the 62nd Design Automation Conference! See you in San Francisco, USA πŸŽ‰!

[2024.12] One first-authored paper has been accepted to IEEE AICAS 2025! See you in Bordeaux, France πŸŽ‰!

[2024.06] My dissertation, Design, logic synthesis and physical implementation of pipeline processor based on RISC-V architecture, has been selected as the excellent graduation project πŸŽ‰!

[2024.02] I will be a Ph.D. student at the University of Virginia in Fall 2024 and have been awarded the UVA Provost's Fellowship πŸŽ‰!